MTS Cache Hierarchy and System Interface Verification Engineer - 83092
Location: Fort Collins
Posted on: February 22, 2021
What You Do At AMD Changes Everything
At AMD, we push the boundaries of what is possible. We believe in
changing the world for the better by driving innovation in
high-performance computing, graphics, and visualization
technologies - building blocks for gaming, immersive platforms, and
the data center.
Developing great technology takes more than talent: it takes
amazing people who understand collaboration, respect, and who will
go the "extra mile" to achieve unthinkable results. It takes people
who have the passion and desire to disrupt the status quo, push
boundaries, deliver innovation, and change the world. If you have
this type of passion, we invite you to take a look at the
opportunities available to come join our team.
This engineer will utilize their technical expertise to assist in
the verification of AMD's next-generation CPU microprocessors.
They will maintain and enhance existing verification test benches
to test cache and system interface functionality, including DFT
features such as MBIST. Work on related projects and/or assignments
as needed, to meet team goals. Write and execute detailed test
plans. Develop quality, timely and cost-effective solutions
independently. Interface with architects and RTL designers. Be
involved in all phases of the project from specification to working
with silicon validation teams. . At this level, they would need to
demonstrate leadership qualities and have excellent time management
A successful person in this role would possess good written and
communication skills and would be able to work in a collaborative
team environment working with architects, RTL designers,
physical-design and silicon validation teams.
- Perform Functional and Design for Test feature verification of
high-speed Microprocessor designs, including development of
infrastructure, directed and random test suites at behavioral RTL
and gate design levels across SoC, Core and block hierarchies.
- Develop environments, infrastructure and test plans to
accommodate both full chip and stand-alone block-level verification
and debug capabilities using simulation tools, debug tools and
programming skills, based on in-depth understanding of the
architecture and HDL/logical design of the microprocessor.
- Participate in development of formal verification
- Develop an automated regression infrastructure setup for
functional verification of highspeed microprocessor designs.
- Collaborate with a dedicated team of engineers to define and
verify DFT microarchitecture for AMD CPUs.
- Work with product test teams during test bring up phase of the
- Based on thorough understanding of the design architecture,
develop, run and debug x86 assembly based directed tests and random
exercisers to validate functionality and testability operation of
the microprocessor design leveraging C/C++/Perl/assembly
programming, logic design and simulation skill set.
- Resolve all simulation discrepancies and assertion responses
for both behavioral and gate level logic models.
- Measure and analyze coverage terms, address exposed weaknesses
to meet design/project quality objectives.
- Develop infrastructure for pattern generation used in post
silicon device validation and characterization.
- When presented with post-silicon issues, replicate design
responses using presilicon infrastructure and provide debug
expertise to ensure complete validation and characterization
- Drive project deliverables/dependencies with
cross-discipline/site RTL, DFT and Implementation design teams
along with product manufacturing teams.
- Prior experience with verification techniques of
- Demonstrated expertise with Verilog HDL.
- Proven programming proficiency in x86 assembly, C/C++ and Perl,
and Ruby languages along with strong logic simulation
- Demonstrated solid understanding of modern computer
architecture including thorough DFT feature knowledge with JTAG
-1149.x, Memory, Logic and I/O Built-In-Self-Test(BIST) and Scan
design(LSSD/MuxD) structures and protocol.
- Familiarity with CMOS transistor design and deep sub-micron
logic and memory fault models, including fault simulation
- Strong understanding of DFT concepts in areas of MBIST (Memory
Built In Self Test) and other related DFT techniques for memory
- Prior knowledge of formal verification tools and techniques a
Preferred BS, MS, PhD In EE/CE
Fort Collins, Colorado
Requisition Number: 83092
Country: United States State: Colorado City: Ft Collins
Job Function: Design
AMD does not accept unsolicited resumes from headhunters,
recruitment agencies or fee based recruitment services. AMD and its
subsidiaries are equal opportunity employers. We consider
candidates regardless of age, ancestry, color, marital status,
medical condition, mental or physical disability, national origin,
race, religion, political and/or third party affiliation, sex,
pregnancy, sexual orientation, gender identity, military or veteran
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Keywords: AMD, Fort Collins , MTS Cache Hierarchy and System Interface Verification Engineer - 83092, Other , Fort Collins, Colorado
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